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Vhdl Record Type Assignment

Hi All,

 

I'm trying to assign an array of records (record elements are of the std_logic_vector type) to a signal of the std_logic_vector type. 

 

Something is going wrong...

 

Here is the signals declaration: 

 

signal dbg_port0 : dbg_reg_t; signal dbg_port1 : dbg_reg_t;
signal bit_vec_dbg_mux_o : bit_vec_rec; 

 

 

Here are the types declarations:

subtype dbg_reg_t is std_logic_vector(31 downto 0); type bit_rec is record v : std_logic; -- bit value vld : std_logic; -- bit valid end record; type bit_vec_rec is array (0 to 31) of bit_rec;

Here is an assignment, which works:

dbg_port0(0) <= bit_vec_dbg_mux_o(0).vld; -- ok

Here is an assignment, which doesn't work:

 

dbg_port0(31 downto 0) <= bit_vec_dbg_mux_o(31 downto 0).v; -- errordbg_port1(31 downto 0) <= bit_vec_dbg_mux_o(31 downto 0).vld; -- error

 

 

So, what's the problem? Why might only a single element of the array be assigned? Why cannot be assigned the whole array of records?

 

 

 

 

 

Thank you!

 

My initial reaction to seeing the aggregate in your default value for pair_in was that there were too many 'others', so I independently wrote one using the record type declaration itself:

And this analyzed successfully. An aggregate has two types of association, positional or named. The above default value expression is positional. With a named association:

You'll notice this bears an uncanny resemblance to the value expression found in Morten's accepted answer's constant declaration, and actually tells the story of compatibility for an aggregate expression.

An aggregate compatible with a record type contains a value expression that is compatible with each element of the record type. This is done for the array elements data and address by providing aggregates for their default values, while WrReq and RdReq are provided with their default values directly.

The extra others statement found in the original attempt would have been appropriate had been a composite type comprised of an array comprised of record type elements.

The LRM (e.g. IEEE Std 1076-1993) has a section on Expressions, a subsection on Aggregates with a further subsection on Record aggregates.

There's also a section on Types, a subsection on Composite types, with a further subsection on Record types.

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